The present invention relates to a semiconductor device manufacturing method by which it is possible to secure voltage resistance between conduction layers used for wiring, to miniaturize the wiring and to facilitate higher integration.
Attendant on miniaturization and higher integration of semiconductor devices, the delay of electrical signals due to the time constant of wiring becomes a serious problem. Therefore, for conduction layers used in a multi-layer wiring step, copper (Cu) wirings have come to be introduced in place of wirings formed by using aluminum (Al) based alloys. Unlike the metallic materials that have been used in the conventional multi-layer wiring structures such as aluminum, copper is difficult to pattern by dry etching. Therefore, there has been generally used the so-called groove wiring technology (for example, the Damascene process) in which wiring grooves are preliminarily formed between layers and then the grooves are filled with copper to form a wiring pattern. Particularly, the method in which contact holes and wiring grooves are preliminarily formed and then the contact holes and the wiring grooves are simultaneously filled with copper (for example, the dual Damascene process) is effective for reducing the number of steps (see, for example, Japanese Patent Laid-open No. Hei 11-045887).
In addition, since an increase in the wiring capacitance leads to a lowering in the speed of the device, fine multi-layer wiring by use of a low-dielectric-constant film as an inter-layer insulation film is indispensable. Examples of the material for the low-dielectric-constant inter-layer insulation film include not only fluorine-containing silicon oxide (FSG) having a dielectric constant of about 3.5 and having hitherto given comparatively good results but also low-dielectric-constant films having a dielectric constant of about 2.7. Examples of the low-dielectric constant films are organic silicon based polymers represented by polyaryl ethers (PAE) and inorganic materials represented by hydrogensilsesquioxane (HSQ) and methylsilsesquioxane (MSQ). In recent years, even introduction of materials provided with a dielectric constant of about 2.2 by making these exemplar materials porous has been tried.
The dual Damascene process, when applied to the low-dielectric-constant inter-layer insulation film, must be a process that can overcome the following technical restrictions.
First, since the composition of the low-dielectric-constant film is close to the composition of the resist used for patterning, the low-dielectric-constant film is liable to be damaged at the time of the resist removing process. Specifically, it is indispensable that the resist peeling treatment after etching is conducted by use of a resist mask, and the resist regenerating treatment in the case where a treated resist pattern does not fulfill the product specifications can be performed without damaging the low-dielectric-constant film.
Next, a problem exists in connection with the application to the so-called borderless structure in which the wiring and the contact holes do not have registration allowances. Attendant on the miniaturization of semiconductor devices, a processing process capable of coping with the borderless structure is a major premise, at least in the multi-layer wirings of 0.18 μm generation and the latter generations. Therefore, even in the case where simultaneous formation of wiring grooves and contact holes by the dual Damascene process is applied to the inter-layer insulation films including the low-dielectric-constant film, a process accompanied by little variations in the via resistance due to misregistration is indispensable.
Additionally, though an etching blocking film must be present near the bottom portions of wiring grooves in order to form the wiring grooves with good depth controllability, insertion of an etching blocking film with a comparatively high dielectric constant as an inter mediate layer leads to an increase in the inter-layer capacitance. Therefore, there is a demand for a dual Damascene process for a low-dielectric-constant film, inter-layer structure with which the increase in capacitance can be suppressed while controlling the formation of wiring grooves.
Dual Damascene processes completed while paying attention to the above-mentioned technical restrictions have been disclosed (see, for example, Japanese Patent Laid-open Nos. 2000-150519 and 2001-44189). In addition, the present inventor et al have devised a dual Damascene process for a low-dielectric-constant film inter-layer structure including an organic film using a three-layer hard mask, as a dual Damascene process for a low-dielectric-constant film inter-layer structure capable of coping with high-performance devices of the 90 nm generation and the latter generations (see, for example, R. Kanamura et al, “Integration of Cu/low-k Dual-Damascene Interconnects with a Porous PAE/SiOC Hybrid Structure for 65 nm-node High Performance eDRAM”, 2003 Symposium on VSI Technology Digest of Technical Papers, pp. 107-108 (2003)).
Now, the problems involved in the case of applying the dual Damascene process to the design rules for fine wiring pitches of the 65 nm generation or the 45 nm generation will be described below, referring to FIGS. 6A to 6H.
As shown in FIG. 6A, on an under insulation film 611 formed on a substrate (not shown), a lower layer wiring 614 of a copper (Cu) film buried wiring structure in which a laminate film composed of an organic film 612 and a silicon oxide (SiO2) film 613, for example, is used as an inter-layer insulation film is formed.
On the silicon oxide film 613, for example, a silicon carbide (SiC) film is formed as an oxidation preventive layer 615 for the Cu film covering the lower layer wiring 614, and a carbon-containing silicon oxide (SiOC) film 616 is formed on the oxidation preventive layer 615. Further, a polyaryl ether (PAE) film, for example, is formed as an organic film 617. Subsequently, a silicon oxide (SiO2) film as a first mask layer 618, a silicon nitride (SiN) film as a second mask layer 619, and a silicon oxide (SiO2) film as a third mask layer 620 are sequentially formed in a laminated form, and a resist pattern 621 for forming wiring grooves is formed on the third mask layer 620.
Next, as shown in FIG. 6B, the resist pattern 621 [see FIG. 6A] is used as an etching mask, and a wiring groove pattern 622 in the third mask layer 620 is formed by a dry etching method. Then, the resist pattern 621 is removed through appropriate after-treatments. Next, a resist pattern 623 for formation of a contact hole pattern is formed. The resist pattern 623 is so formed as to overlap, at least partly, the wiring groove pattern 622. The resist pattern 623 is formed to be aligned relative to the lower layer wiring 614 or the wiring groove pattern 622; in this case, a region 624 of the so-called borderless structure in relation to the wiring groove pattern 622 is generated due to misregistrations which can be generated on a lithography process basis or dispersions of the dimensions of the layers.
Subsequently, as shown in FIG. 6C, the resist pattern 623 [see FIG. 6B] is used as an etching mask, and contact holes 625 are formed in the third mask layer 620 and the second mask layer 619 and the first mask layer 618 by a dry etching method, and then the contact holes 625 are extended to the PAE film 617. Here, the resist pattern 623 can be removed simultaneously with the etching treatment of the PAE film 617. Additionally, the resist pattern 623 gradually recedes during the opening of the contact holes 625 in the PAE film 617, and it is possible to obtain a good opening shape due to the presence of the second mask 6layer 619 composed of silicon nitride.
Next, as shown in FIG. 6D, the third mask layer 620 provided with the wiring groove pattern 622 is used, and the wiring groove pattern 622 is extendedly formed in the second mask layer 619 by a dry etching method. In addition, in the etching step of the second mask layer 619 using the third mask layer 620, the SiOC film 616 exposed at bottom portions of the contact holes can be opened to an intermediate extent. Since the etching selectivity ratio (SiN/SiOC) relative to the SiOC film under the above-mentioned etching conditions can be set to be slightly less than 1, in the case of etching the second mask layer 619 of silicon nitride having a thickness of 50 nm, the contact holes 625 are extendedly formed in the SiOC film 616 in the manner of including a required over-etching amount, and are opened to a depth of about 80 nm.
Subsequently, as shown in FIG. 6E, the contact holes 625 are formed in the SiOC film 616 remaining between the contact hole layers. Here, the first mask layer 618 remaining in the wiring groove regions is simultaneously removed by use of the second mask layer 619 provided with the wiring groove pattern, whereby wiring grooves 629 are formed. In this instance, as shown in FIG. 6F, in the region where the contact holes 625 and the upper layer wiring grooves 629 are in a borderless structure and where the adjacent wiring grooves 629 are arranged in a minimum space, the inter-wiring space is locally narrowed. This corresponds to the PAE film 617 between the wiring groove 629 (on the left side in the figure) and the wiring groove 629 (on the right side in the figure).
Thereafter, the PAE film 617 remaining at bottom portions of the wiring grooves 629 is etched to extendingly form the wiring grooves 629, and the SiC film 615 present at bottom portions of the contact holes 625 extendedly formed is etched, whereby the contact holes 625 are further extended. Thus, a predetermined dual Damascene processing is completed. Then, the narrow space region generated due to misregisterations in the contact hole patterning and dispersions of the dimensions may be narrowed, but not widened, due to an increase of shoulder etch. Incidentally, the second mask layer 619 remaining outside the wiring groove regions is removed in the process of etching the SiC film 615 present at bottom portions of the contact holes 625.
Thereafter, etching debris remaining on side walls of the wiring grooves 629 and the contact holes 625 and the denatured copper layer at bottom portions of the contact holes 625 are cleaned by an after-treatment using an appropriate chemical liquid and a hydrogen annealing treatment. Then, as shown in FIG. 6G, a Ta film as a barrier metal layer 632 is formed, for example, by a sputtering method, and a copper (Cu) film 633 is built up by an electroplating method or a sputtering method, whereby the wiring grooves 629 and the contact holes 625 are filled with a conduction film.
Further, the portions unnecessary as wiring pattern, of the barrier metal layer 632 and the copper film 633 are removed by a chemical mechanical polishing (CMP) method. As a result, as shown in FIG. 6H, upper layer wirings 634 composed of the copper film 633 are formed, and a multi-layer wiring structure of a dual Damascene structure is obtained. In addition, like the lower layer wirings 614, an SiC film 635, for example, as an oxidation preventive layer is formed on the dual Damascene wirings 634. However, at the narrow space portions generated due to misregistrations in the patterning of the contact holes 625 or dispersions of the dimensions, regions 636 of unsatisfactory isolation between the wirings (for example, between the upper layer wiring 634 (on the left side in the figures) and the upper layer wiring 634 (on the right side in the figures)) are formed.
It has been confirmed that the multi-layer wiring produced by the dual Damascene process as above shows a lowering in the yield due to short-circuit defects between the wiring and the adjacent different-potential wiring, since the regions 636 of unsatisfactory isolation between the wirings are generated locally. It has also been found that even in the case where the different-potential wirings are isolated in the range of operation of the semiconductor device, initial defects due to insufficient dielectric strength and abrasion troubles may sometimes be generated in the case of an isolation width of 25 nm or below and in use conditions thereafter.